RISC-V Projects

Protecting RISCV Against Timing Side-Channel Attacks

  • Supervisor(s): Prof. Avi Mendelson
  • Requirements: Computer Architecture (236267), knowledge on HDL development (optional), knowldge of hardware security (optional)
  • Project document
  • Status: available
Timing side-channel attacks are based on the observation that if the execution time of an execution path depends on the value it executes, the time can be used to predict the value.
This project is based on a paper, “Secure and Speculative Core,” but this time, we would like to implement the idea as part of a RISCV architecture implemented over FPGA.
The student can choose to focus on the implementation or to extend the work (and so to make it a research project).
As part of the project, the student will extend their knowledge of how processors work, how to develop models that will run over FPGA, and more. 
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RISCV-based Mechanism to Recover from Security Attacks

  • Supervisor(s): Prof. Avi Mendelson
  • Requirements: Computer Architecture (236267), course / knowledge in security attacks
  • Project document
  • Status: available
Suppose you have a mechanism that allows you to detect security attacks. What can you do?
Critical systems cannot be stopped if a security attack happens. An alternative is to create checkpoints and rewind the system to the last known safe-point.
This project aims to develop such a mechanism and add it to an existing RISCV implementation.
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Security Counters for RISCV processor

Recently we proposed and implemented the notion of Security counter as part of RISCV processor. The idea is to be able to count the number of events that occur within an interval of time or an interval of code. In this project, you are requested to extend this idea and to write software that can demonstrate its capabilities.
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SDR-based extension to RISCV processor

SDR is a unique data type, of 1024 or 2024 bits long, but it is guaranteed that only up to 2% of its bits can be set (i.e., set to 1). In this project, we would like to develop a RISC-V-based architecture that has a set of SDR registers with a few unique operations among them.
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